[llvm] [AArch64] Fix for misched-branch-targets.mir test (PR #68424)

[Anatoly Trosinenko via llvm-commits]

https://github.com/atrosinenko created https://github.com/llvm/llvm-project/pull/68424

Fix test failure in non-assertion builds introduced by f1b2dd2a111f038420b3f69d4ce0b3b3f245c873.

>From 58c01f79d9a762ef95a64f2f2e1d5634a69d0014 Mon Sep 17 00:00:00 2001
From: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Date: Fri, 6 Oct 2023 18:31:21 +0300
Subject: [PATCH] [AArch64] Fix for misched-branch-targets.mir test

Fix test failure in non-assertion builds introduced by
f1b2dd2a111f038420b3f69d4ce0b3b3f245c873.
---
 llvm/test/CodeGen/AArch64/misched-branch-targets.mir | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/llvm/test/CodeGen/AArch64/misched-branch-targets.mir b/llvm/test/CodeGen/AArch64/misched-branch-targets.mir
index f32c1e964f97356..ce11b095f6176ab 100644
--- a/llvm/test/CodeGen/AArch64/misched-branch-targets.mir
+++ b/llvm/test/CodeGen/AArch64/misched-branch-targets.mir
@@ -1,6 +1,9 @@
 # RUN: llc -o - -run-pass=machine-scheduler -misched=shuffle %s | FileCheck %s
 # RUN: llc -o - -run-pass=postmisched %s | FileCheck %s
 
+; REQUIRES: asserts
+; -misched=shuffle is only available with assertions enabled
+
 # Check that instructions that are recognized as branch targets by BTI
 # are not reordered by machine instruction schedulers.