[llvm] Late temporal divergence lowering for SDAG (PR #67033)

[via llvm-commits]

petar-avramovic wrote:

> > I understand now, that does look like an issue but I don't have a test for that. I assumed that IR passes would move both %0 and %1 outside the loop.
> 
> There are many reasons that a instruction cannot be sunk. For this situation, it is much easier to make a test using mir. I don't think it is too hard to get the MIR output of the test in the PR before machine-sink and add one scalar instruction S_ADD to show the issue.

Ugh, sgpr reg class is too strong, if you sink sgpr instruction it is still uniform because of 
```
    if (TRI.isUniformReg(MRI, RBI, op.getReg()))
      continue;
```
It was meant to be marked as divergent because of temporal divergence. This breaks uniformity info after the loop.

https://github.com/llvm/llvm-project/pull/67033