[llvm] Late temporal divergence lowering for SDAG (PR #67033)

[via llvm-commits]

petar-avramovic wrote:

 > There are many reasons that a instruction cannot be sunk. For this situation, it is much easier to make a test using mir. I don't think it is too hard to get the MIR output of the test in the PR before machine-sink and add one scalar instruction S_ADD to show the issue.

Added mir test in https://github.com/llvm/llvm-project/pull/67456 
switched to using register classes and opcodes instead of machine-uniformity-analysis-info and left a fixme comment


https://github.com/llvm/llvm-project/pull/67033