[llvm] [InlineAsm] add comments for NumOperands and ConstraintType (PR #67474)

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git-clang-format --diff ac466c75258888a212e52a4616e287dc4ec6a68b 00ed0bb58992322ab0d87f79a4b2cfdeefd7546c -- llvm/include/llvm/IR/InlineAsm.h llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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View the diff from clang-format here.
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diff --git a/llvm/include/llvm/IR/InlineAsm.h b/llvm/include/llvm/IR/InlineAsm.h
index fdb76b3ec969..e7b3cf0b98f4 100644
--- a/llvm/include/llvm/IR/InlineAsm.h
+++ b/llvm/include/llvm/IR/InlineAsm.h
@@ -277,16 +277,18 @@ public:
   // on INLINEASM and INLINEASM_BR MachineInstr's.
   //
   // The encoding of Flag is currently:
-  //   Bits 2-0 - A Kind::* value indicating the kind of the operand. (KindField)
-  //   Bits 15-3 - The number of SDNode operands associated with
+  //   Bits 2-0 - A Kind::* value indicating the kind of the operand.
+  //   (KindField) Bits 15-3 - The number of SDNode operands associated with
   //               this inline assembly operand. Once lowered to MIR, this
   //               represents the number of MachineOperands necessary to
   //               refer to a MachineOperandType::MO_FrameIndex. (NumOperands)
   //   Bit 31 - determines if this is a matched operand. (IsMatched)
   //   If bit 31 is set:
-  //     Bits 30-16 - The operand number that this operand must match. (MatchedOperandNo)
+  //     Bits 30-16 - The operand number that this operand must match.
+  //     (MatchedOperandNo)
   //   Else if bits 2-0 are Kind::Mem:
-  //     Bits 30-16 - A ConstraintCode:: value indicating the original constraint code. (MemConstraintCode)
+  //     Bits 30-16 - A ConstraintCode:: value indicating the original
+  //     constraint code. (MemConstraintCode)
   //   Else:
   //     Bits 30-16 - The register class ID to use for the operand. (RegClass)
   //

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https://github.com/llvm/llvm-project/pull/67474