[llvm] [InlineAsm] add comments for NumOperands and ConstraintType (PR #67474)
Nick Desaulniers via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 27 08:42:35 PDT 2023
https://github.com/nickdesaulniers updated https://github.com/llvm/llvm-project/pull/67474
>From 00ed0bb58992322ab0d87f79a4b2cfdeefd7546c Mon Sep 17 00:00:00 2001
From: Nick Desaulniers <ndesaulniers at google.com>
Date: Tue, 26 Sep 2023 11:38:19 -0700
Subject: [PATCH 1/2] [InlineAsm] add comments for NumOperands and
ConstraintType
Splitting up patches for #20571. I found these comments generally useful
to add and not predicated on those changes. Hopefully they help future
travelers.
---
llvm/include/llvm/IR/InlineAsm.h | 4 +++-
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 8 ++++++--
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/llvm/include/llvm/IR/InlineAsm.h b/llvm/include/llvm/IR/InlineAsm.h
index 0c0389871fc2f9b..fdb76b3ec969705 100644
--- a/llvm/include/llvm/IR/InlineAsm.h
+++ b/llvm/include/llvm/IR/InlineAsm.h
@@ -279,7 +279,9 @@ class InlineAsm final : public Value {
// The encoding of Flag is currently:
// Bits 2-0 - A Kind::* value indicating the kind of the operand. (KindField)
// Bits 15-3 - The number of SDNode operands associated with
- // this inline assembly operand. (NumOperands)
+ // this inline assembly operand. Once lowered to MIR, this
+ // represents the number of MachineOperands necessary to
+ // refer to a MachineOperandType::MO_FrameIndex. (NumOperands)
// Bit 31 - determines if this is a matched operand. (IsMatched)
// If bit 31 is set:
// Bits 30-16 - The operand number that this operand must match. (MatchedOperandNo)
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 6aaaa2f68638c7d..0ba79098b7dd724 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -5803,11 +5803,15 @@ TargetLowering::ConstraintWeight
/// If there are multiple different constraints that we could pick for this
/// operand (e.g. "imr") try to pick the 'best' one.
-/// This is somewhat tricky: constraints fall into four classes:
-/// Other -> immediates and magic values
+/// This is somewhat tricky: constraints (TargetLowering::ConstraintType) fall
+/// into seven classes:
/// Register -> one specific register
/// RegisterClass -> a group of regs
/// Memory -> memory
+/// Address -> a symbolic memory reference
+/// Immediate -> immediate values
+/// Other -> magic values (such as "Flag Output Operands")
+/// Unknown -> something we don't recognize yet and can't handle
/// Ideally, we would pick the most specific constraint possible: if we have
/// something that fits into a register, we would pick it. The problem here
/// is that if we have something that could either be in a register or in
>From d805a88faec76134d065a76dd0083086a6dca456 Mon Sep 17 00:00:00 2001
From: Nick Desaulniers <ndesaulniers at google.com>
Date: Wed, 27 Sep 2023 08:42:21 -0700
Subject: [PATCH 2/2] manually reflow comments to appease the formatter
---
llvm/include/llvm/IR/InlineAsm.h | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/llvm/include/llvm/IR/InlineAsm.h b/llvm/include/llvm/IR/InlineAsm.h
index fdb76b3ec969705..93be75d9e6aa97a 100644
--- a/llvm/include/llvm/IR/InlineAsm.h
+++ b/llvm/include/llvm/IR/InlineAsm.h
@@ -277,16 +277,19 @@ class InlineAsm final : public Value {
// on INLINEASM and INLINEASM_BR MachineInstr's.
//
// The encoding of Flag is currently:
- // Bits 2-0 - A Kind::* value indicating the kind of the operand. (KindField)
+ // Bits 2-0 - A Kind::* value indicating the kind of the operand.
+ // (KindField)
// Bits 15-3 - The number of SDNode operands associated with
// this inline assembly operand. Once lowered to MIR, this
// represents the number of MachineOperands necessary to
// refer to a MachineOperandType::MO_FrameIndex. (NumOperands)
- // Bit 31 - determines if this is a matched operand. (IsMatched)
+ // Bit 31 - Determines if this is a matched operand. (IsMatched)
// If bit 31 is set:
- // Bits 30-16 - The operand number that this operand must match. (MatchedOperandNo)
+ // Bits 30-16 - The operand number that this operand must match.
+ // (MatchedOperandNo)
// Else if bits 2-0 are Kind::Mem:
- // Bits 30-16 - A ConstraintCode:: value indicating the original constraint code. (MemConstraintCode)
+ // Bits 30-16 - A ConstraintCode:: value indicating the original
+ // constraint code. (MemConstraintCode)
// Else:
// Bits 30-16 - The register class ID to use for the operand. (RegClass)
//
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