[PATCH] D158759: [RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp:92
+            MI.getOpcode() != RISCV::PseudoVSETIVLI) {
+          const TargetRegisterClass *RC = MRI->getRegClass(Reg);
+          if (!(RC && RC->contains(RISCV::X0))) {
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dtcxzyw wrote:
> craig.topper wrote:
> > Why are we using MRI->getRegClass instead of TII->getRegClass like AArch64?
> It protects defs with reg class `GPRNoX0` being rewritten to x0.
> See also https://reviews.llvm.org/D158759?id=554599#inline-1539364.
> For inst `li a3, 32`, `MRI->getRegClass` returns `GPRNoX0` while `TTI->getRegClass` returns `GPR`.
> 
> I have a separate patch to address this: https://github.com/llvm/llvm-project/pull/65934
> 
Does the `!Desc.mayLoad() && !Desc.mayStore() &&
          !Desc.hasUnmodeledSideEffects()` check already prevent that?


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  https://reviews.llvm.org/D158759/new/

https://reviews.llvm.org/D158759