[PATCH] D158759: [RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused

[Yingwei Zheng via Phabricator via llvm-commits]

dtcxzyw updated this revision to Diff 556907.
dtcxzyw added a comment.

- Rebase
- Use `TargetInstrInfo::getRegClass`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158759/new/

https://reviews.llvm.org/D158759

Files:
  llvm/lib/Target/RISCV/CMakeLists.txt
  llvm/lib/Target/RISCV/RISCV.h
  llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
  llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/CodeGen/RISCV/O3-pipeline.ll
  llvm/test/CodeGen/RISCV/atomic-rmw-discard.ll
  llvm/test/CodeGen/RISCV/branch.ll
  llvm/test/CodeGen/RISCV/double-mem.ll
  llvm/test/CodeGen/RISCV/float-mem.ll
  llvm/test/CodeGen/RISCV/half-mem.ll
  llvm/test/CodeGen/RISCV/local-stack-slot-allocation.ll
  llvm/test/CodeGen/RISCV/machinelicm-address-pseudos.ll
  llvm/test/CodeGen/RISCV/mem.ll
  llvm/test/CodeGen/RISCV/mem64.ll
  llvm/test/CodeGen/RISCV/rvv/localvar.ll
  llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
  llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir

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