[PATCH] D158759: [RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp:92
+            MI.getOpcode() != RISCV::PseudoVSETIVLI) {
+          const TargetRegisterClass *RC = MRI->getRegClass(Reg);
+          if (!(RC && RC->contains(RISCV::X0))) {
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Why are we using MRI->getRegClass instead of TII->getRegClass like AArch64?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158759/new/

https://reviews.llvm.org/D158759