[PATCH] D158759: [RISCV] Add a pass to rewrite rd to x0 for non-computational instrs whose return values are unused
Yingwei Zheng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sat Sep 16 09:53:54 PDT 2023
dtcxzyw marked an inline comment as done.
dtcxzyw added inline comments.
================
Comment at: llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir:365
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v8
- ; CHECK-NEXT: $x0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
+ ; CHECK-NEXT: [[PseudoVSETVLI:%[0-9]+]]:gprnox0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
----------------
craig.topper wrote:
> This looks like a regression
It will be addressed by the following pass `RISCVDeadRegisterDefinitions`. This test only runs the pass `RISCVInsertVSETVLI`.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D158759/new/
https://reviews.llvm.org/D158759
More information about the llvm-commits
mailing list