[llvm] [DAGCombiner][RISCV] Prefer to sext i32 non-negative values (PR #65984)

Yingwei Zheng via llvm-commits llvm-commits at lists.llvm.org
Fri Sep 15 05:05:42 PDT 2023

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dtcxzyw wrote:

https://github.com/llvm/llvm-project/blob/c464896dbe2ad5a8641a675fff525656e88be38a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp#L1375-L1377

https://github.com/llvm/llvm-project/pull/65984

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