[llvm] [DAGCombiner][RISCV] Prefer to sext i32 non-negative values (PR #65984)

[Craig Topper via llvm-commits]

topperc wrote:

> > InstCombine does the same thing. 
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> I think you mean ISel. https://github.com/llvm/llvm-project/blob/231aa0f2120552b474bf86d5ff6721a6c555fdc3/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp#L6072
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> > Do we need a reverse transform to turn zext into sext explicitly? Or perhaps an isel pattern?
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> It is unsafe to turn `zext` into `sext`. Why not just prevent tuning `zext` into `sext`?
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visitSExt in InstCombine will turn sext into zext. That code will happen before DAGCombine. The DAGCombine change will only effect sext that is created during SelectionDAG. sext that already existed in IR may get changed by InstCombine.

So my question was do we need to change zext to sext if the sign bit of the input is known to be 0 by computeKnownBits.

https://github.com/llvm/llvm-project/pull/65984