[llvm] [DAGCombiner][RISCV] Prefer to sext i32 non-negative values (PR #65984)

[Yingwei Zheng via llvm-commits]

dtcxzyw wrote:

Diff: https://github.com/llvm/llvm-project/compare/main...dtcxzyw:llvm-project:zext-to-sext
Evaluation result: https://github.com/dtcxzyw/llvm-ci/pull/627

It seems better to sext a non-negative value on riscv64. But this change broke some regression tests.


https://github.com/llvm/llvm-project/pull/65984