[PATCH] D158704: [PowerPC] Implement SchedModel for Power7

[Qiu Chaofan via Phabricator via llvm-commits]

qiucf updated this revision to Diff 556622.
qiucf marked 4 inline comments as done.
qiucf added a comment.

- Update VSX instructions according to new version UM
- Rename issue ports
- Add `IsISA2_07` to unsupported features
- VMX has only one port


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158704/new/

https://reviews.llvm.org/D158704

Files:
  llvm/lib/Target/PowerPC/PPCScheduleP7.td
  llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll
  llvm/test/CodeGen/PowerPC/aix-lower-jump-table-mir.ll
  llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-char.ll
  llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-double.ll
  llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-float.ll
  llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-int.ll
  llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-largeaccess.ll
  llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-longlong.ll
  llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-short.ll
  llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-double.ll
  llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-float.ll
  llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-int.ll
  llvm/test/CodeGen/PowerPC/aix-tls-le-ldst-longlong.ll
  llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large.ll
  llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large32.ll
  llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc.ll
  llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc32.ll
  llvm/test/CodeGen/PowerPC/aix-vec-arg-spills-mir.ll
  llvm/test/CodeGen/PowerPC/aix-vec-arg-spills.ll
  llvm/test/CodeGen/PowerPC/aix-vector-stack-caller.ll
  llvm/test/CodeGen/PowerPC/aix-vsx-splatimm.ll
  llvm/test/CodeGen/PowerPC/all-atomics.ll
  llvm/test/CodeGen/PowerPC/bswap-load-store.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-p8vector.ll
  llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-move-tofrom-regs.ll
  llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll
  llvm/test/CodeGen/PowerPC/cc.ll
  llvm/test/CodeGen/PowerPC/crbit-asm.ll
  llvm/test/CodeGen/PowerPC/crbits.ll
  llvm/test/CodeGen/PowerPC/expand-foldable-isel.ll
  llvm/test/CodeGen/PowerPC/expand-isel.ll
  llvm/test/CodeGen/PowerPC/fma-mutate.ll
  llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
  llvm/test/CodeGen/PowerPC/fpscr-intrinsics.ll
  llvm/test/CodeGen/PowerPC/fsel.ll
  llvm/test/CodeGen/PowerPC/i1-ext-fold.ll
  llvm/test/CodeGen/PowerPC/ifcvt.ll
  llvm/test/CodeGen/PowerPC/load-and-splat.ll
  llvm/test/CodeGen/PowerPC/machine-combiner.ll
  llvm/test/CodeGen/PowerPC/peephole-align.ll
  llvm/test/CodeGen/PowerPC/ppc-crbits-onoff.ll
  llvm/test/CodeGen/PowerPC/ppc-partword-atomic.ll
  llvm/test/CodeGen/PowerPC/ppc64-P9-vabsd.ll
  llvm/test/CodeGen/PowerPC/ppc64-calls.ll
  llvm/test/CodeGen/PowerPC/ppcf128-endian.ll
  llvm/test/CodeGen/PowerPC/pr61882.ll
  llvm/test/CodeGen/PowerPC/recipest.ll
  llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll
  llvm/test/CodeGen/PowerPC/sjlj.ll
  llvm/test/CodeGen/PowerPC/sms-remark.ll
  llvm/test/CodeGen/PowerPC/subreg-postra.ll
  llvm/test/CodeGen/PowerPC/test-vector-insert.ll
  llvm/test/CodeGen/PowerPC/tls-store2.ll
  llvm/test/CodeGen/PowerPC/unal-vec-ldst.ll
  llvm/test/CodeGen/PowerPC/unal4-std.ll
  llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll
  llvm/test/CodeGen/PowerPC/vavg.ll
  llvm/test/CodeGen/PowerPC/vec-icmpeq-v2i64-p7.ll
  llvm/test/CodeGen/PowerPC/vec-min-max.ll
  llvm/test/CodeGen/PowerPC/vec_cmpd_p7.ll
  llvm/test/CodeGen/PowerPC/vec_shuffle_p8vector.ll
  llvm/test/CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll
  llvm/test/CodeGen/PowerPC/vsx.ll
  llvm/test/CodeGen/PowerPC/widen-vec-correctly-be.ll