[PATCH] D158704: [PowerPC] Implement SchedModel for Power7

[ChenZheng via Phabricator via llvm-commits]

shchenz added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCScheduleP7.td:33
+                             PairedVectorMemops, IsISA3_0,
+                             PCRelativeMemops, IsISA3_1, IsISAFuture];
 }
----------------
What rules do we take to add unsupported features here? I believe we are missing lots of CPU features defined in PPC.td.


================
Comment at: llvm/lib/Target/PowerPC/PPCScheduleP7.td:51
+  // Executing simple FX, complex FX, permute and 4-way SIMD single-precision FP ops
+  def P7_VMX: ProcResource<2>;
+  def P7_VPM: ProcResource<2> {
----------------
I checked P7_bookIV version 2.1, in sections 4.1.3, it says there is only 1 VMX unit:

> One VMX execution unit capable of executing simple FX, complex FX, permute and 4-way SIMD single-precision FP ops

```
 Twelve execution units
– Two symmetric load/store units (LSU), also capable of executing simple fixed-point ops
– Two symmetric fixed-point units (FXU)
– Four floating-point units (FPU), implemented as two 2-way SIMD operations for double- and
single-precision. Scalar binary floating point instructions can only use two FPUs.
– One VMX execution unit capable of executing simple FX, complex FX, permute and 4-way SIMD
single-precision FP ops
– One decimal floating-point unit (DFU)
– 1 Branch execution unit (BR)
– 1 CR Logical execution unit (CRL)
```


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Comment at: llvm/lib/Target/PowerPC/PPCScheduleP7.td:60
+
+  def P7_PORT_1 : ProcResource<2>;
+  def P7_PORT_2 : ProcResource<2>;
----------------
use meaningful names please.


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Comment at: llvm/lib/Target/PowerPC/PPCScheduleP7.td:64
+  def P7_PORT_4 : ProcResource<1>;
+  def P7_PORT_5 : ProcResource<1>;
+
----------------
```
Out of order issue of up to 8 operations into the following 8 issue ports
– Two load or store operations
– Two fixed-point operations
– Two issue ports shared by two floating-point, two VSX, two VMX and one DFP ops
– One branch operation
– One condition register operation
```


================
Comment at: llvm/lib/Target/PowerPC/PPCScheduleP7.td:218
+  // NOTE: VSX scalar instructions are not listed in Book IV, define them the
+  // same as equivalent float instructions.
+  def : InstRW<[P7_ScalarFPU_6C, P7_DISP_FP], (instrs
----------------
hmm, in the above version, I see latency info for vsx scalar instructions.


Repository:
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  https://reviews.llvm.org/D158704/new/

https://reviews.llvm.org/D158704