[PATCH] D158704: [PowerPC] Implement SchedModel for Power7

[ChenZheng via Phabricator via llvm-commits]

shchenz accepted this revision as: shchenz.
shchenz added a comment.
This revision is now accepted and ready to land.

LGTM with a small fix in one LIT.

I assume 1: you fixed all the LIT failures except the auto generated cases(the summary of the patch needs update). 2: you checked that the performance impact of this patch is positive for -mcpu=pwr7.



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Comment at: llvm/lib/Target/PowerPC/PPCScheduleP7.td:33
+                             PairedVectorMemops, IsISA3_0,
+                             PCRelativeMemops, IsISA3_1, IsISAFuture];
 }
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shchenz wrote:
> What rules do we take to add unsupported features here? I believe we are missing lots of CPU features defined in PPC.td.
hmm, OK, let use this setting for now. I think we may need a similar approach in SystemZ arch. That's more clear and robust.


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Comment at: llvm/test/CodeGen/PowerPC/aix-vector-stack-caller.ll:85
 declare i32 @vec_callee_stack(...)
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; LITERAL: {{.*}}
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Fix the broken case.


Repository:
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  https://reviews.llvm.org/D158704/new/

https://reviews.llvm.org/D158704