[PATCH] D158163: [RISCV] Narrow types of index operand matched pattern (shl_vl (zext_vl), C)

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:11201
+bool isVMV_V_X_VLOfConstant(SDValue N, APInt &SplatVal) {
+  if (N.getOpcode() == RISCVISD::VMV_V_X_VL &&
+      isa<ConstantSDNode>(N->getOperand(1))) {
----------------
vmv_v_x_vl also supports a passthru operand which may not be undef.  You need to check for that to be sure you actually have a splat here.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158163/new/

https://reviews.llvm.org/D158163