[PATCH] D158163: [RISCV] Narrow types of index operand matched pattern (shl_vl (zext_vl), C)

[Liao Chunyu via Phabricator via llvm-commits]

liaolucy added a comment.

In D158163#4643531 <https://reviews.llvm.org/D158163#4643531>, @reames wrote:

> I want to suggest a different approach here.  I think this should be a combine on MGATHER (and variants), not a combine on the RISCV specific nodes.  It might make sense to have this be a target specific combine, but I don't think it needs to be a combine on custom nodes.
>
> Looking at one of your tests, I see this state immediately before lowering:
>
>       t15: v8i64 = zero_extend t6
>       t17: v8i64 = BUILD_VECTOR Constant:i64<1>, Constant:i64<1>, Constant:i64<1>, Constant:i64<1>, Constant:i64<1>, Constant:i64<1>, Constant:i64<1>, Constant:i64<1>
>     t18: v8i64 = shl t15, t17
>   t27: v8i16,ch = masked_gather<(load unknown-size, align 2), signed unscaled offset> t0, t12, t9, t2, t18, TargetConstant:i64<1>
>
> The MGATHER node supports scaled offsets, and allows the index type to differ from the native type (i.e. there's implicit extend on the operand).  The later seems like it's the right tool here.  See refineIndexType in DAGCombine for an example of some code which is related.  Basically, we're just inverting the zero_extend placement, and then running that transform.  We might even be able to do this in fully generic code.

Thanks for the advice and trying to understand

0. Base GAG

      t15: v8i64 = zero_extend t6
      t17: v8i64 = BUILD_VECTOR Constant:i64<1>, Constant:i64<1>, Constant:i64<1>, Constant:i64<1>, Constant:i64<1>, Constant:i64<1>, Constant:i64<1>, Constant:i64<1>
    t18: v8i64 = shl t15, t17
  t27: v8i16,ch = masked_gather<(load unknown-size, align 2), signed unscaled offset> t0, t12, t9, t2, t18, TargetConstant:i64<1>

1. inverting the zero_extend placement:

       t29: v8i8 = BUILD_VECTOR Constant:i8<1>, Constant:i8<1>, Constant:i8<1>, Constant:i8<1>, Constant:i8<1>, Constant:i8<1>, Constant:i8<1>, Constant:i8<1>
      t30: v8i8 = shl t6, t29
    t31: v8i64 = zero_extend t30
  t27: v8i16,ch = masked_gather<(load unknown-size, align 2), signed unscaled offset> t0, t12, t9, t2, t31, TargetConstant:i64<1>

2. Use RVV indexed load/store instructions zero extend their indexed operand to XLEN. Delete zero_extend

       t29: v8i8 = BUILD_VECTOR Constant:i8<1>, Constant:i8<1>, Constant:i8<1>, Constant:i8<1>, Constant:i8<1>, Constant:i8<1>, Constant:i8<1>, Constant:i8<1>
      t30: v8i8 = shl t6, t29
  t27: v8i16,ch = masked_gather<(load unknown-size, align 2), signed unscaled offset> t0, t12, t9, t2, t30, TargetConstant:i64<1>

But the conversion 0 -> 1 seems to be unequal. https://alive2.llvm.org/ce/z/-acjAs
Please help correct me if I'm not understanding something correctly, thanks!


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158163/new/

https://reviews.llvm.org/D158163