[PATCH] D159265: [AArch64] Remove copy instruction between uaddlv and urshr
    JinGu Kang via Phabricator via llvm-commits 
    llvm-commits at lists.llvm.org
       
    Fri Sep  8 01:33:45 PDT 2023
    
    
  
jaykang10 added inline comments.
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:23169
+                  DAG.getConstant(0, DL, MVT::i64));
+  SDValue BITCAST = DAG.getNode(ISD::BITCAST, DL, MVT::v1i64, EXTRACT_SUBVEC);
+
----------------
dmgreen wrote:
> I'm pretty sure this needs to be an AArch64ISD::NVCAST, not a BITCAST. The BITCAST will swap the 0th and 1st lanes into the i64, we need to keep them inorder.
Ah, I did not know we do not need `rev` instruction here.
Let me change BITCAST to NVCAST.
Thanks for letting me know.
CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D159265/new/
https://reviews.llvm.org/D159265
    
    
More information about the llvm-commits
mailing list