[llvm] [RISCV] Lower constant build_vectors with few non-sign bits via vsext (PR #65648)

[Philip Reames via llvm-commits]

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@@ -3456,6 +3456,27 @@ static SDValue lowerBuildVectorOfConstants(SDValue Op, SelectionDAG &DAG,
   if (SDValue Res = lowerBuildVectorViaDominantValues(Op, DAG, Subtarget))
     return Res;
 
+  // IF the number of signbits allows, see if we can lower as a <N x i8>.
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preames wrote:

Nope, fixed.

https://github.com/llvm/llvm-project/pull/65648