[llvm] [RISCV][MC] Implement evaluateBranch for auipc+jalr pairs (PR #65480)

[Alexander Richardson via llvm-commits]

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@@ -0,0 +1,18 @@
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s | \
+# RUN:     llvm-objdump -d -M no-aliases --no-show-raw-insn - | \
+# RUN:     FileCheck %s
+
+## Test multiple interleaved auipc/jalr pairs
+# CHECK: auipc t0, 0
+1: auipc t0, %pcrel_hi(bar)
+# CHECK: auipc t1, 0
+2: auipc t1, %pcrel_hi(bar)
+# CHECK: jalr ra, 16(t0) <bar>
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arichardson wrote:

I'd also add a test here with an unhandled instruction e.g. mul between the auipc and a jalr that clobbers the destination register. Also need to be conservative for jumps etc since those could clobber registers (and we don't know the exact calling convention here since it could be hand-written assembly code)

https://github.com/llvm/llvm-project/pull/65480