[llvm] [RISCV][MC] Implement evaluateBranch for auipc+jalr pairs (PR #65480)
Alexander Richardson via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 6 19:54:33 PDT 2023
================
@@ -114,10 +114,40 @@ static MCTargetStreamer *createRISCVNullTargetStreamer(MCStreamer &S) {
namespace {
class RISCVMCInstrAnalysis : public MCInstrAnalysis {
+ std::optional<int64_t> GPRState[31];
+
+ void setGPRState(unsigned Reg, int64_t Value) {
+ assert(Reg >= RISCV::X0 && Reg <= RISCV::X31 && "Invalid GPR reg");
+
+ if (Reg != RISCV::X0)
+ GPRState[Reg - RISCV::X1] = Value;
+ }
+
+ std::optional<int64_t> getGPRState(unsigned Reg) const {
+ assert(Reg >= RISCV::X0 && Reg <= RISCV::X31 && "Invalid GPR reg");
+
+ if (Reg == RISCV::X0)
+ return 0;
+ return GPRState[Reg - RISCV::X1];
+ }
+
public:
explicit RISCVMCInstrAnalysis(const MCInstrInfo *Info)
: MCInstrAnalysis(Info) {}
+ void resetState() override {
+ std::fill(std::begin(GPRState), std::end(GPRState), std::nullopt);
+ }
+
+ void updateState(const MCInst &Inst, uint64_t Addr) override {
+ switch (Inst.getOpcode()) {
+ case RISCV::AUIPC:
+ setGPRState(Inst.getOperand(0).getReg(),
+ Addr + (Inst.getOperand(1).getImm() << 12));
+ break;
+ }
----------------
arichardson wrote:
This does not look safe to me, you will also have to invalidate the state for the destination register(s) for unhandled instructions otherwise you might report a wrong value.
https://github.com/llvm/llvm-project/pull/65480
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