[PATCH] D159267: [AArch64] Remove copy instruction between uaddlv and dup

[JinGu Kang via Phabricator via llvm-commits]

jaykang10 added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:5322
+    EVT ResVT = Op.getValueType();
+    if (ResVT == MVT::i32 && (OpVT == MVT::v8i8 || OpVT == MVT::v16i8)) {
+      // In order to avoid insert_subvector, used v4i32 than v2i32.
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efriedma wrote:
> This could be extended to i16 uaddlv as well, but we can leave that for a followup, I guess.
Yep, it seems there is no pattern for dup(extract_element) --> duplane with v8i16.
Let's handle the type with other patch.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:5325
+      SDValue UADDLV =
+          DAG.getNode(AArch64ISD::UADDLV, dl, MVT::v4i32, Op.getOperand(1));
+      SDValue EXTRACT_VEC_ELT =
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dmgreen wrote:
> An MVT::v8i16 with an extract might be a more natural representation for UADDLV that produces a h register.
The uaddlv intrinsic's result type with v8i8 and v16i8 is i32 rather than i16 so we need to return i32 type as the extract vector element's result. 


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:8716
         ISD::INTRINSIC_WO_CHAIN, DL, MVT::i32,
         DAG.getConstant(Intrinsic::aarch64_neon_uaddlv, DL, MVT::i32), CtPop);
 
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dmgreen wrote:
> Can you change this to generate a UADDLV directly?
Maybe, we could use UADDLV here.
Let's check it with other patch.


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Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:331
 def SDT_AArch64DupLane   : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
+def SDT_AArch64UAddlv   : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVec<1>]>;
 def SDT_AArch64Insr  : SDTypeProfile<1, 2, [SDTCisVec<0>]>;
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dmgreen wrote:
> I think this can be the same as SDT_AArch64uaddlp
Let me use SDT_AArch64uaddlp.


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  https://reviews.llvm.org/D159267/new/

https://reviews.llvm.org/D159267