[PATCH] D159443: [AArch64] Fix schedmodel zero latency moves for Neoverse V2

[Ricardo Jesus via Phabricator via llvm-commits]

rjj created this revision.
rjj added reviewers: SjoerdMeijer, dmgreen, david-arm.
Herald added subscribers: gbedwell, hiraditya, kristof.beyls.
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rjj requested review of this revision.
Herald added a project: LLVM.

Model some register-to-register move operations and move immediate
operations as ``zero latency moves'', as described in the Software
Optimisation Guide (SOG), §4.12:

https://developer.arm.com/documentation/PJDOC-466751330-593177/r0p2/

NB I've assumed there's a mistake in the SOG on p. 63 in the following
instructions:

mov  h1, wzr
mov  h1, xzr
mov  s1, wzr
mov  d1, xzr

(The `mov' should be an `fmov'.)


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D159443

Files:
  llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
  llvm/lib/Target/AArch64/AArch64SchedPredNeoverse.td
  llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-basic-instructions.s
  llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-zero-lat-movs.s

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