[PATCH] D158759: [RISCV] Add a pass to rewrite rd to x0 for instrs whose return values are unused

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll:12396
 ; RV64ZVE32F-NEXT:    lbu a2, 0(a2)
-; RV64ZVE32F-NEXT:    li a3, 32
+; RV64ZVE32F-NEXT:    li zero, 32
 ; RV64ZVE32F-NEXT:    vmv.s.x v12, a2
----------------
craig.topper wrote:
> I don't know why it didn't get removed either, but its not ok for this pass to change this instruction.
It only became dead after InsertVSETVLI and we don't run DCE after that.

@craig.topper Why isn't this legal?  If the instruction is dead, this does appear to be a valid instruction encoding?  I don't see anything in the spec about addi zero, zero, imm being reserved or anything.  


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158759/new/

https://reviews.llvm.org/D158759