[PATCH] D158759: [RISCV] Add a pass to rewrite rd to x0 for instrs whose return values are unused

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Aug 30 08:58:15 PDT 2023

craig.topper added inline comments.

Comment at: llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp:66
+      // FIXME: Remove the following check after D158759 to handle
+      // PseudoVSETVLI/PseudoVSETIVLI
+      if (MI.isPseudo())
dtcxzyw wrote:
> I cannot handle `PseudoVSETVLI/PseudoVSETIVLI` now since the diff is too large (about 300+ KLOCs with full context).
> Could I remove this check after committing this patch?
If you're getting a lot of changes, it's probably a bug. It's not safe to change the destination to X0 for `RISCV::PseudoVSETVLIX0` which is a different instruction than PseudoVSETVLI/PseudoVSETIVLI. Without an explicit check for it, that instruction it would be included.

Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll:12396
 ; RV64ZVE32F-NEXT:    lbu a2, 0(a2)
-; RV64ZVE32F-NEXT:    li a3, 32
+; RV64ZVE32F-NEXT:    li zero, 32
 ; RV64ZVE32F-NEXT:    vmv.s.x v12, a2
I don't know why it didn't get removed either, but its not ok for this pass to change this instruction.

  rG LLVM Github Monorepo



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