[PATCH] D158759: [RISCV] Add a pass to rewrite rd to x0 for instrs whose return values are unused

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Aug 31 10:46:00 PDT 2023

craig.topper added inline comments.

Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll:12396
 ; RV64ZVE32F-NEXT:    lbu a2, 0(a2)
-; RV64ZVE32F-NEXT:    li a3, 32
+; RV64ZVE32F-NEXT:    li zero, 32
 ; RV64ZVE32F-NEXT:    vmv.s.x v12, a2
reames wrote:
> craig.topper wrote:
> > I don't know why it didn't get removed either, but its not ok for this pass to change this instruction.
> It only became dead after InsertVSETVLI and we don't run DCE after that.
> @craig.topper Why isn't this legal?  If the instruction is dead, this does appear to be a valid instruction encoding?  I don't see anything in the spec about addi zero, zero, imm being reserved or anything.  
Isn't it one of the hint encodings? It won't crash, but it might cause unintended effects from hint. If it was an ORI it could be a non-temporal hint for example. If it was an AUIPC it would become a landing pad from the CFI proposal.

  rG LLVM Github Monorepo



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