[PATCH] D158874: [RISCV] Form vmv.s.f/x from single element splats via DAG combine

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:13913
+    // If VL is 1 and the scalar value won't benefit from immediate, we can
+    // use vmv.s.x.  Only do this only if legal to avoid breaking i64 sext(i32)
+    // patterns on rv32..
----------------
I don't think we need "only" twice in the second sentence


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:13917
+    if (isOneConstant(VL) && EltWidth <= Subtarget.getXLen() &&
+        (!Const || isNullConstant(Scalar) || !isInt<5>(Const->getSExtValue())))
+      return DAG.getNode(RISCVISD::VMV_S_X_VL, DL, VT, Passthru, Scalar, VL);
----------------
Const->isZero()


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td:592
+                         [(riscv_vfmv_v_f_vl undef, node:$op, srcvalue),
+                          (riscv_vfmv_s_f_vl undef, node:$op, 1)]>;
 
----------------
Why do we check the vl for riscv_vfmv_s_f_vl, but we don't check the VL for RISCVISD::VMV_S_X_VL in selectVSplat?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158874/new/

https://reviews.llvm.org/D158874