[PATCH] D159029: [RISCV] Correct scheduling information for WriteVIRedMinMaxV in RISCVSchedSiFive7.td.
Wang Pengcheng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 28 19:51:09 PDT 2023
wangpc accepted this revision.
wangpc added a comment.
This revision is now accepted and ready to land.
LGTM.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D159029/new/
https://reviews.llvm.org/D159029
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