[PATCH] D159029: [RISCV] Correct scheduling information for WriteVIRedMinMaxV in RISCVSchedSiFive7.td.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Aug 28 22:47:54 PDT 2023
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG23fef2cc673a: [RISCV] Correct scheduling information for WriteVIRedMinMaxV in… (authored by craig.topper).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D159029/new/
https://reviews.llvm.org/D159029
Files:
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
Index: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -774,11 +774,12 @@
foreach sew = SchedSEWSet<mx>.val in {
defvar Cycles = SiFive7GetReductionCycles<mx, sew>.c;
defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
- let Latency = Cycles, ReleaseAtCycles = [Cycles] in
- defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [SiFive7VA],
- mx, sew, IsWorstCase>;
- defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [SiFive7VA],
- mx, sew, IsWorstCase>;
+ let Latency = Cycles, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [SiFive7VA],
+ mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [SiFive7VA],
+ mx, sew, IsWorstCase>;
+ }
}
}
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D159029.554188.patch
Type: text/x-patch
Size: 1075 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230829/b0873b03/attachment.bin>
More information about the llvm-commits
mailing list