[PATCH] D159029: [RISCV] Correct scheduling information for WriteVIRedMinMaxV in RISCVSchedSiFive7.td.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D159029#4623433 <https://reviews.llvm.org/D159029#4623433>, @wangpc wrote:

> I remember that the reasom why we added separate Scheds for min/max reductions is that your downstream needs to give different scheduling for min/max from other reductions in D155108 <https://reviews.llvm.org/D155108>.
> Is it right for this processor?

Yes. For this processor min/max is the same as add/and/or/xor. We need it split for a processor we haven't upstreamed yet.


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