[PATCH] D159029: [RISCV] Correct scheduling information for WriteVIRedMinMaxV in RISCVSchedSiFive7.td.

[Wang Pengcheng via Phabricator via llvm-commits]

wangpc added a comment.

I remember that the reasom why we added separate Scheds for min/max reductions is that your downstream needs to give different scheduling for min/max from other reductions in D155108 <https://reviews.llvm.org/D155108>.
Is it right for this processor?


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https://reviews.llvm.org/D159029