[PATCH] D159029: [RISCV] Correct scheduling information for WriteVIRedMinMaxV in RISCVSchedSiFive7.td.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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The 'let' with the Latency and Cycles from the previous defm should
apply to this one as well. Introduce a scope around the two defms.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D159029

Files:
  llvm/lib/Target/RISCV/RISCVSchedSiFive7.td


Index: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -774,11 +774,12 @@
   foreach sew = SchedSEWSet<mx>.val in {
     defvar Cycles = SiFive7GetReductionCycles<mx, sew>.c;
     defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
-    let Latency = Cycles, ReleaseAtCycles = [Cycles] in
-    defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [SiFive7VA],
-                                   mx, sew, IsWorstCase>;
-    defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [SiFive7VA],
-                                   mx, sew, IsWorstCase>;
+    let Latency = Cycles, ReleaseAtCycles = [Cycles] in {
+      defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [SiFive7VA],
+                                     mx, sew, IsWorstCase>;
+      defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [SiFive7VA],
+                                     mx, sew, IsWorstCase>;
+    }
   }
 }
 


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