[PATCH] D158824: [RISCV][MC] MC layer support for xcvmem and xcvelw extensions
Liao Chunyu via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 27 18:11:37 PDT 2023
liaolucy updated this revision to Diff 553822.
liaolucy added a comment.
1. core-v -> CORE-V to be consistent with other places
2. rebase
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D158824/new/
https://reviews.llvm.org/D158824
Files:
llvm/docs/RISCVUsage.rst
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/MC/RISCV/attribute-arch.s
llvm/test/MC/RISCV/corev/XCVelw-invalid.s
llvm/test/MC/RISCV/corev/XCVelw-valid.s
llvm/test/MC/RISCV/corev/XCVmem-invalid.s
llvm/test/MC/RISCV/corev/XCVmem-valid.s
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