[PATCH] D158824: [RISCV][MC] MC layer support for xcvmem and xcvelw extensions

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2512
+  if (parseRegister(Operands, true).isSuccess()) {
+    // Parse memory base register if present (core-v only)
+    if (getSTI().getFeatureBits()[RISCV::FeatureVendorXCVmem]) {
----------------
core-v -> CORE-V to be consistent with other places?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158824/new/

https://reviews.llvm.org/D158824