[PATCH] D158824: [RISCV][MC] MC layer support for xcvmem and xcvelw extensions

[Jim Lin via Phabricator via llvm-commits]

Jim added a comment.

It is also needed to add pre-defined macro test in clang/test/Preprocessor/riscv-target-features.c



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Comment at: llvm/docs/RISCVUsage.rst:273
+``XCVelw``
+  LLVM implements `version 1.0.0 of the CORE-V Event load custom instructions specification <https://github.com/openhwgroup/cv32e40p/blob/master/docs/source/instruction_set_extensions.rst>`_ by OpenHW Group.  All instructions are prefixed with `cv.mac` as described in the specification. These instructions are only available for riscv32 at this time.
+
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prefixed with `cv.` ?


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td:565
+class CVStore_rr_inc<bits<3> funct3, bits<7> funct7, dag outs, dag ins,
+                        string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
----------------
Indent.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td:581
+class CVStore_rr<bits<3> funct3, bits<7> funct7, dag outs, dag ins,
+                    string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
----------------
Indent.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td:632
+    : RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd), 
+        (ins GPRMem:$rs1, simm12:$imm12), opcodestr, "$rd, ${imm12}(${rs1})">;
+
----------------
Indent.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td:636
+    mayLoad = 1, mayStore = 0 in {
+  //Event load
+  def CV_ELW : CVLoad_ri<0b011, "cv.elw">;
----------------
// Event load


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Comment at: llvm/test/MC/RISCV/corev/XCVelw-valid.s:2
+# RUN: llvm-mc -triple=riscv32 --mattr=+xcvelw -show-encoding %s \
+# RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INSTR
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+xcvelw < %s \
----------------
Indent is not the same with others.


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https://reviews.llvm.org/D158824