[PATCH] D158364: [DAG] SimplifyDemandedBits - if we're only demanding the signbits, a SMIN/SMAX node can be simplified to a OR/AND node respectively.

[Noah Goldstein via Phabricator via llvm-commits]

goldstein.w.n added a comment.

Also I think this also works for `umax` / `umin` (although inverted): https://alive2.llvm.org/ce/z/UX_NYn
There is a fair bit of common codes between, maybe a this should also come with a helper like
`simplifyMinMaxWithDemandedBits`.


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https://reviews.llvm.org/D158364