[PATCH] D158364: [DAG] SimplifyDemandedBits - if we're only demanding the signbits, a SMIN/SMAX node can be simplified to a OR/AND node respectively.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon planned changes to this revision.
RKSimon added a comment.

I'll update this to add umin/umax handling


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D158364/new/

https://reviews.llvm.org/D158364