[PATCH] D158396: [RISCV] Add missed fcsr spill and restore in interrupt

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:752
+
+    BuildMI(MBB, LastFrameDestroy, DL, TII->get(RISCV::CSRRW))
+        .addReg(RISCV::X0, RegState::Define)
----------------
craig.topper wrote:
> Can we use the WriteFRM and ReadFRM pseudo instructions?
Nevermind. it's fcsr not just frm


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D158396/new/

https://reviews.llvm.org/D158396