[PATCH] D158396: [RISCV] Add missed fcsr spill and restore in interrupt

Tue Aug 22 02:08:05 PDT 2023

wangpc added a comment.

In D158396#4605518 <https://reviews.llvm.org/D158396#4605518>, @craig.topper wrote:

> In D158396#4605474 <https://reviews.llvm.org/D158396#4605474>, @wangpc wrote:
>
>> I am not against this patch, just one thought: is it possible that we add `FCSR` as a `RISCVReg` in `RISCVRegisterInfo.td` (new RegisterClass may be needed), and add it to `CSR_Interrupt` in `RISCVCallingConv.td`? The spill/restore can be done by `CSRRS` for this kind of CSRs.
>> This may reduce the code if we need spill/restore more CSRs in the future.
>
> Will that need to create a virtual register and scavenge a GPR since we can't load/store a GPR from memory directly?

I posted the patch D158492 <https://reviews.llvm.org/D158492> though I'm not sure it's worthy as it increases stack size and adds complexity to code.

Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D158396/new/

https://reviews.llvm.org/D158396