[PATCH] D158396: [RISCV] Add missed fcsr spill and restore in interrupt

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D158396#4605474 <https://reviews.llvm.org/D158396#4605474>, @wangpc wrote:

> I am not against this patch, just one thought: is it possible that we add `FCSR` as a `RISCVReg` in `RISCVRegisterInfo.td` (new RegisterClass may be needed), and add it to `CSR_Interrupt` in `RISCVCallingConv.td`? The spill/restore can be done by `CSRRS` for this kind of CSRs.
> This may reduce the code if we need spill/restore more CSRs in the future.

Will that need to create a virtual register and scavenge a GPR since we can't load/store a GPR from memory directly?



================
Comment at: llvm/lib/Target/RISCV/RISCVFrameLowering.cpp:752
+
+    BuildMI(MBB, LastFrameDestroy, DL, TII->get(RISCV::CSRRW))
+        .addReg(RISCV::X0, RegState::Define)
----------------
Can we use the WriteFRM and ReadFRM pseudo instructions?


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https://reviews.llvm.org/D158396