[PATCH] D158396: [RISCV] Add missed fcsr spill and restore in interrupt

[Wang Pengcheng via Phabricator via llvm-commits]

wangpc added a comment.

I am not against this patch, just one thought: is it possible that we add `FCSR` as a `RISCVReg` in `RISCVRegisterInfo.td` (new RegisterClass may be needed), and add it to `CSR_Interrupt` in `RISCVCallingConv.td`? The spill/restore can be done by `CSRRS` for this kind of CSRs.
This may reduce the code if we need spill/restore CSRs.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D158396/new/

https://reviews.llvm.org/D158396