[PATCH] D157417: [RISCV][SelectionDAG] Lower shuffles as bitrotates with vror.vi when possible

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

In D157417#4602937 <https://reviews.llvm.org/D157417#4602937>, @luke wrote:

> But if there's still some codegen issues to be addressed, should we defer handling non-zvbb archs to a later patch?

I'm fine with staging in this way.  I mostly brought it up because it might result in a different code structure.

LGTM

Follow ups worth exploring:

- Can we use slide lowering when no-zbb?
- Can we handle vector.reverse via tree of rotates?  Either only with zbb, or always?



================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll:192
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, ma
 ; CHECK-NEXT:    vid.v v9
----------------
As a follow up, it's worth noting this can be done as two rotates.  One at 32 SEW by 16, and one at SEW by 8.  The later is a brev8.  


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