[PATCH] D157417: [RISCV][SelectionDAG] Lower shuffles as bitrotates with vror.vi when possible

Mon Aug 21 02:55:07 PDT 2023

luke added a comment.

In D157417#4596043 <https://reviews.llvm.org/D157417#4596043>, @craig.topper wrote:

> Why isn't this constant folded
>
>   +; CHECK-NEXT:    vmv.v.i v9, 0
>   +; CHECK-NEXT:    li a0, 16
>   +; CHECK-NEXT:    vwsubu.vx v10, v9, a0
>
> This and feels unnecessary. This shift only uses the lower 5 bits
>
>   +; CHECK-NEXT:    li a1, 31
>   +; CHECK-NEXT:    vsetvli zero, zero, e32, m1, ta, ma
>   +; CHECK-NEXT:    vand.vx v9, v10, a1
>   +; CHECK-NEXT:    vsrl.vv v9, v8, v9

I put both sequences through llvm-mca, and on the sifive-x280 model it seems like the rotate sequence has better throughput. F28770219: rotate-mca-output.txt <https://reviews.llvm.org/F28770219>
 But if there's still some codegen issues to be addressed, should we defer handling non-zvbb archs to a later patch?

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