[PATCH] D157417: [RISCV][SelectionDAG] Lower shuffles as bitrotates with vror.vi when possible

[Jim Lin via Phabricator via llvm-commits]

Jim added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll:4
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh -verify-machineinstrs < %s | FileCheck %s -check-prefixes=CHECK
+; RUN: llc -mtriple=riscv32 -mattr=+v,+zvfh,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s -check-prefixes=ZVBB_V
+; RUN: llc -mtriple=riscv64 -mattr=+v,+zvfh,+experimental-zvbb -verify-machineinstrs < %s | FileCheck %s -check-prefixes=ZVBB_V
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In testcases for RISC-V, I always saw that use '-' not '_' underline in check-prefixes.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D157417/new/

https://reviews.llvm.org/D157417