[PATCH] D158163: [RISCV] Narrow types of index operand matched pattern (shl_vl (zext_vl), C)

[Liao Chunyu via Phabricator via llvm-commits]

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Similar to D154687 <https://reviews.llvm.org/D154687>, we can optimize fix length vector.

lowerBUILD_VECTOR lower BUILD_VECTOR to RISCVISD::VMV_V_X_VL.
Add isVMV_V_X_VLOfConstant, which implements similar functionality of isBuildVectorOfConstantSDNodes.

extract_subvector + insert_subvector can be optimize in 
visitINSERT_SUBVECTOR <https://github.com/llvm/llvm-project/blob/main/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L25601>.
Optimization is advanced for better type narrowing.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D158163

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll

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