[PATCH] D158163: [RISCV] Narrow types of index operand matched pattern (shl_vl (zext_vl), C)

[Yeting Kuo via Phabricator via llvm-commits]

fakepaper56 added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:11229
+  // just use the input to the extract.
+  if (N1.getOpcode() == ISD::INSERT_SUBVECTOR) {
+    SDValue N10 = N1.getOperand(0);
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The combine code exists in `DAGCombiner::visitINSERT_SUBVECTOR`. Why do we need this here?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D158163/new/

https://reviews.llvm.org/D158163