[PATCH] D158086: [RISCV] Check floating point vector instruction with SEW=64 is valid when vsetvl insertion

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

I would suggest an initial patch which simply disabled the problematic logic for zve64f.  Adding the additional inference state can be a separate follow on.  In particularly, you currently don't have test coverage for the optimization bits.



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Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:1534
   MRI = &MF.getRegInfo();
+  hasVInstructionsF64 = ST.hasVInstructionsF64();
 
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Instead of using a global, please just check the property of the subtarget as the call sites.  Much easier to read.


Repository:
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https://reviews.llvm.org/D158086