[PATCH] D158086: [RISCV] Check floating point vector instruction with SEW=64 is valid when vsetvl insertion

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp:210
+        1,      // SEW can be changed as long as it's greater
+                // than or equal to the original value, but must
+                // less than 64
----------------
"must less" -> "must be less"


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D158086/new/

https://reviews.llvm.org/D158086