[llvm] 61ab106 - [RISCV] Add tune features of preferred function/loop align
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Mon Aug 14 21:05:10 PDT 2023
Author: wangpc
Date: 2023-08-15T12:04:12+08:00
New Revision: 61ab106f82d187a30e83dcd4ce5832c3802a5438
URL: https://github.com/llvm/llvm-project/commit/61ab106f82d187a30e83dcd4ce5832c3802a5438
DIFF: https://github.com/llvm/llvm-project/commit/61ab106f82d187a30e83dcd4ce5832c3802a5438.diff
LOG: [RISCV] Add tune features of preferred function/loop align
D144048 has added preferred function and loop alignment to
RISCVSubtarget, but now we need to set them manually for
different processors.
Tune features that set preferred function/loop align to
[2, 64] bytes (align 1 is not here since the min align is 2)
are added. These features can be used in processor
definitions.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D157832
Added:
Modified:
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/test/CodeGen/RISCV/align-loops.ll
llvm/test/CodeGen/RISCV/align.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 8aeaa11bae5b8e..fb33b1e3a6d5f1 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -925,3 +925,12 @@ def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
"AllowTaggedGlobals",
"true", "Use an instruction sequence for taking the address of a global "
"that allows a memory tag in the upper address bits">;
+
+foreach align = [2, 4, 8, 16, 32, 64] in {
+ def TunePrefFunctionAlignment # align :
+ SubtargetFeature<"pref-func-align-" # align, "PrefFunctionAlignment",
+ "Align(" # align # ")", "Set preferred function alignment to " # align # " bytes">;
+ def TunePrefLoopAlignment # align :
+ SubtargetFeature<"pref-loop-align-" # align, "PrefLoopAlignment",
+ "Align(" # align # ")", "Set preferred loop alignment to " # align # " bytes">;
+}
diff --git a/llvm/test/CodeGen/RISCV/align-loops.ll b/llvm/test/CodeGen/RISCV/align-loops.ll
index efa03992b6277f..5ef78c74d03532 100644
--- a/llvm/test/CodeGen/RISCV/align-loops.ll
+++ b/llvm/test/CodeGen/RISCV/align-loops.ll
@@ -1,6 +1,8 @@
; RUN: llc < %s -mtriple=riscv64 | FileCheck %s
; RUN: llc < %s -mtriple=riscv64 -align-loops=16 | FileCheck %s -check-prefix=ALIGN_16
; RUN: llc < %s -mtriple=riscv64 -align-loops=32 | FileCheck %s -check-prefix=ALIGN_32
+; RUN: llc < %s -mtriple=riscv64 -mattr=+pref-loop-align-16 | FileCheck %s -check-prefix=ALIGN_16
+; RUN: llc < %s -mtriple=riscv64 -mattr=+pref-loop-align-32 | FileCheck %s -check-prefix=ALIGN_32
declare void @foo()
diff --git a/llvm/test/CodeGen/RISCV/align.ll b/llvm/test/CodeGen/RISCV/align.ll
index 5807fc14efc292..1fb4585f8422aa 100644
--- a/llvm/test/CodeGen/RISCV/align.ll
+++ b/llvm/test/CodeGen/RISCV/align.ll
@@ -2,6 +2,8 @@
; RUN: | FileCheck %s -check-prefix=RV32I
; RUN: llc -mtriple=riscv32 -mattr=+c -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32C
+; RUN: llc -mtriple=riscv32 -mattr=+pref-func-align-32 -verify-machineinstrs < %s \
+; RUN: | FileCheck %s -check-prefix=ALIGN-32
; RUN: llc -filetype=obj -mtriple=riscv32 < %s -o %t
; RUN: llvm-readelf -S %t | FileCheck %s --check-prefixes=SEC,SEC-I
; RUN: llc -filetype=obj -mtriple=riscv32 -mattr=+c < %s -o %t
@@ -16,6 +18,8 @@ define void @foo() {
;RV32I: foo:
;RV32C: .p2align 1
;RV32C: foo:
+;ALIGN-32: .p2align 5
+;ALIGN-32: foo:
entry:
ret void
}
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