[llvm] ac00cca - [RISCV] Fix assertion when passing f64 vectors via integer registers

[via llvm-commits]

Author: wangpc
Date: 2023-08-15T12:11:08+08:00
New Revision: ac00cca3d9c6c3e9118ebbe47aa5b3ba1ee7404f

URL: https://github.com/llvm/llvm-project/commit/ac00cca3d9c6c3e9118ebbe47aa5b3ba1ee7404f
DIFF: https://github.com/llvm/llvm-project/commit/ac00cca3d9c6c3e9118ebbe47aa5b3ba1ee7404f.diff

LOG: [RISCV] Fix assertion when passing f64 vectors via integer registers

The vector arguments are split but assignments won't be pending.

Fixes #64645

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D157847

Added: 
    llvm/test/CodeGen/RISCV/pr64645.ll

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index bf96fe097645aa..24351a14eefe09 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -15169,8 +15169,7 @@ bool RISCV::CC_RISCV(const DataLayout &DL, RISCVABI::ABI ABI, unsigned ValNo,
   // Handle passing f64 on RV32D with a soft float ABI or when floating point
   // registers are exhausted.
   if (UseGPRForF64 && XLen == 32 && ValVT == MVT::f64) {
-    assert(!ArgFlags.isSplit() && PendingLocs.empty() &&
-           "Can't lower f64 if it is split");
+    assert(PendingLocs.empty() && "Can't lower f64 if it is split");
     // Depending on available argument GPRS, f64 may be passed in a pair of
     // GPRs, split between a GPR and the stack, or passed completely on the
     // stack. LowerCall/LowerFormalArguments/LowerReturn must recognise these

diff  --git a/llvm/test/CodeGen/RISCV/pr64645.ll b/llvm/test/CodeGen/RISCV/pr64645.ll
new file mode 100644
index 00000000000000..44dce5aabd2242
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/pr64645.ll
@@ -0,0 +1,39 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=riscv32 -mattr=+zdinx -verify-machineinstrs -target-abi=ilp32 < %s \
+; RUN:   | FileCheck %s
+
+define <2 x double> @v2f64(<2 x double> %x, <2 x double> %y) nounwind {
+; CHECK-LABEL: v2f64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    sw a4, 8(sp)
+; CHECK-NEXT:    sw a5, 12(sp)
+; CHECK-NEXT:    lw a4, 8(sp)
+; CHECK-NEXT:    lw a5, 12(sp)
+; CHECK-NEXT:    sw a0, 8(sp)
+; CHECK-NEXT:    sw a1, 12(sp)
+; CHECK-NEXT:    lw a0, 8(sp)
+; CHECK-NEXT:    lw a1, 12(sp)
+; CHECK-NEXT:    sw a6, 8(sp)
+; CHECK-NEXT:    sw a7, 12(sp)
+; CHECK-NEXT:    lw a6, 8(sp)
+; CHECK-NEXT:    lw a7, 12(sp)
+; CHECK-NEXT:    sw a2, 8(sp)
+; CHECK-NEXT:    sw a3, 12(sp)
+; CHECK-NEXT:    lw a2, 8(sp)
+; CHECK-NEXT:    lw a3, 12(sp)
+; CHECK-NEXT:    fadd.d a2, a2, a6
+; CHECK-NEXT:    fadd.d a0, a0, a4
+; CHECK-NEXT:    sw a0, 8(sp)
+; CHECK-NEXT:    sw a1, 12(sp)
+; CHECK-NEXT:    lw a0, 8(sp)
+; CHECK-NEXT:    lw a1, 12(sp)
+; CHECK-NEXT:    sw a2, 8(sp)
+; CHECK-NEXT:    sw a3, 12(sp)
+; CHECK-NEXT:    lw a2, 8(sp)
+; CHECK-NEXT:    lw a3, 12(sp)
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
+  %1 = fadd <2 x double> %x, %y
+  ret <2 x double> %1
+}